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Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
0 . 8 V G C 2 ( 1 + sCA × RA )
s ( CA + Cq ) ? 1 +
? ( 1 + sRA × Cq )
C 5
C 12 =
( 2 π × C 5 × R 3 × f P 3 ) - 1
12 nF
= = 53 . 3 pF
2 π × 12 nF × 20 k ? × 150 kHz - 1
Use 47pF.
Linear-Regulator Controllers
OUT2 Voltage Selection
The MAX8513/MAX8514 OUT2 positive linear regula-
tor’s output voltage is set by connecting a resistive-
divider from OUT2 to FB2 to GND. The resistors in the
divider are selected to set the minimum output current
(I OUT2_MIN ). For the Typical Applications Circuit (Figure
5 or Figure 6), the feedback resistors are set to R5 =
340 ? and R6 = 160 ? , where R5 is the resistor from
OUT2 to FB2 and R6 is the resistor from FB2 to GND.
These values set the minimum output current to
≈ 4.5mA, which works well with many MOSFETS.
In general,
the feedback resistors (R5 and R6) set the output-volt-
age reference point as well as the minimum load.
The loop gain for the positive LDO output using an
NMOS transistor is:
×
V OUT 2 ? sC OUT 2 ?
? g C ?
where C OUT2 is C6 in the Typical Applications Circuits .
G C2 is the transconductance of the internal amplifier
(0.21S typ), and a dominant pole at a low frequency is
created from this transconductance and the compen-
sation capacitor (C A in the Typical Applications Circuits
+ Q3’s gate capacitance (C q )). A second pole occurs
due to C OUT2 and the transconductance of Q3 (g C ).
This transconductance varies from a minimum g C(MIN)
occurring at minimum load to a maximum g C(MAX)
occurring at maximum load. To calculate the g C at any
load current, the typical forward transconductance can
be extracted from the MOSFET’s data sheet (gfs), as
I OUT 2 _ MIN =
I OUT 2 _ MAX
333
well as the current at which it is measured (IDfs). The
g C(MIN) and g C(MAX) can be calculated as:
Select R5 and R6 so:
g C ( MAX ) = gfs
I OUT 2(MAX )
IDfs
0.8V
R 6
= I OUT 2 _ MIN
g C ( MIN ) = gfs
I OUT 2(MIN)
IDfs
Poles occur at:
R 5 = R 6 × ? OUT 2 - 1 ?
? V ?
? 0 . 8 V ?
f PMAX =
g C ( MAX )
2 π × C OUT 2
OUT2 Stability
A transconductance amplifier drives the gate of the
and f PMIN =
g C ( MIN )
2 π × C OUT 2
g C ( MIN ) = OUT 2 MIN
NMOS transistor (Q3 in the Typical Applications
Circuits ), with current proportional to the error signal
multiplied by the amplifier ’s transconductance. The
error signal is the difference between V FB2 and the
internal 0.8V reference. V SUP2 , the supply voltage for
the transconductance amplifier, must be at least 1V
greater than the maximum required gate voltage
(V DRV2 ). The output pass transistor (Q3) buffers the
If only a minimum gfs is given, initially assume the max-
imum is twice the minimum.
When using a bipolar transistor, the g C(MAX) and
g C(MIN) occur at the following:
I
V T
DRV2 signal to produce the desired output voltage
(V OUT2 ). The output capacitor (C6 in the Typical
Applications Circuits ) helps bypass the output, while
g C ( MAX ) =
I OUT 2 MAX
V T
where V T is the thermal voltage, 26mV.
______________________________________________________________________________________
27
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